This invention relates to the testing of large scale integrated (LSI) circuits, very large scale integrated (VLSI) circuits and fault tolerant systems implemented with such LSI or VLSI circuits using logic scan design (LSD). In particular, this invention provides for the insertion of programmable transient and intermittent faults into each VLSI chip individually or in combination on a module within a system for verifying fault detection.
The insertion of permanent faults into LSI and VLSI circuit devices or systems is described in J. K. Mathewes, Jr. et al., U.S. Pat. No. 4,669,081 issued May 26, 1987 and assigned to the present assignee, the specification thereof being incorporated by reference herein. This patent teaches providing programmable fault insertion circuitry within a large scale integrated circuit to insert permanent fault types such as "stuck at one" and "stuck at zero" faults. The faults are inserted into functional logic which have all internal storage elements functioning as shift register latches that can be serially accessed allowing the internal states to be observed and controlled.
A well known technique for testing LSI devices and systems employing LSI devices using shift register latches to transform sequential circuits into combinational circuits is known as Level Sensitive Scan Design (LSSD) and it is described in U.S. Pat. Nos. 3,761,695, 3,783,254, 7,784,907 and in the publication "A Logic Design Structure for LSI Testability" by E. B. Eichelberger and T. W. Williams, 14th Design Automation Conference Proceedings, IEEE Computer Society, June 20-22, 1977, pages 462-468. In a system employing LSSD, a logic system is defined as being "level sensitive" if, and only if, the steady state response to any allowed input state change is independent of the circuit and wire delays within the system. Also, if an input stage change involves the changing of more than one input signal, then the response must be independent of the order in which they change. A level sensitive system is assumed to operate as a result of a sequence of allowed input changes with sufficient time lapse between changes to allow the system to stabilize in the new internal state. Thus, LSSD testing is performed by shifting test data via a scan input into a serial chain of logic on an LSI device having storage elements implemented with shift register latches, applying test vectors to the primary inputs of the device under test, and shifting the data out resulting from the applied test vectors via a scan output to compare it to known good test data.
Besides permanent type faults such as "stuck at one" and "stuck-at-zero" in VLSI circuits there are other classes of faults such as transient and intermittent faults which are nonpermanent faults. These nonpermanent faults may also occur on circuit boards interconnecting VLSI circuits and result in unreliable operation of the VLSI circuits and the systems in which they are used. Even in fault tolerant systems transient and intermittent faults may cause incorrect system operations; hence, the ability to test for and detect such nonpermanent faults is very important.
Manual techniques have been used for inserting permanent faults, but they tend to be time-consuming since operator intervention is required to configure the system for each fault or subset of a total fault set to be tested. Generally it is difficult to synchronize the fault insertion with the desired system state of operation. Critical timing paths may be degraded to a marginal or inoperable state by manual techniques used to inject faults whereby the test results may be affected or the analysis may be incomplete. Manual techniques for simulating transient and intermittent faults have similar disadvantages.
In addition to the stuck at one and stuck-at-zero types of faults, other types of faults exist such as a stuck-open fault, a wired-AND bridging fault and a wired-OR bridging fault. A stuck-open fault represents a high impedance and no logic voltage level on a signal line whereas a stuck at one represents the constant presence of a logic level voltage. Bridging faults result from signal lines shorting together and result in a mixing of different signals causing incorrect circuit operation.